Organic laminate substrates, for example printed circuit boards and chip carriers, have been and continue to be developed for many applications. These are expected to displace ceramic substrates in many chip carrier applications, because of reduced cost and enhanced electrical performance. The use of a multi-layered interconnect structure such as an organic, laminate chip carrier for interconnecting a semiconductor chip to a printed circuit board in an electronic package introduces many challenges, one of which is the reliability of the connection joints between the semiconductor chip and the organic chip carrier and another of which is the reliability of the connection joints between the organic chip carrier and the printed circuit board.
As semiconductor chip input/output (I/O) counts increase beyond the capability of peripheral lead devices and as the need for both semiconductor chip and printed circuit board miniaturization increases, area array interconnects are the preferred method for making large numbers of connections between a semiconductor chip and an organic chip carrier and between the organic chip carrier and a printed circuit board. If the coefficient of thermal expansion (CTE) of the semiconductor chip, the organic chip carrier, and the printed circuit board are substantially different from one another, industry standard semiconductor chip array interconnections to the organic chip carrier can exhibit high stress during operation (thermal cycling). Similarly, the industry standard ball grid array (BGA) interconnections between the organic chip carrier and printed circuit board can also exhibit high stress during operation. Significant reliability concerns may then become manifest by failure of the connections or even failure of the integrity of the semiconductor chip (chip cracking). These reliability concerns significantly inhibit design flexibility. For example, semiconductor chip sizes may be limited or interconnect sizes, shapes and spacing may have to be customized beyond industry standards to reduce these stresses. These limitations may limit the electrical performance advantages of the organic electronic package or add significant cost to the electronic package. Typically a semiconductor chip has a CTE of 2–3 parts per million per degree Celsius (ppm/° C.) while a standard printed circuit board has a much greater CTE of 17–20 ppm/° C.
One example of an organic chip carrier designed to overcome such CTE and related problems is defined in U.S. Pat. No. 6,351,393 (J. S. Kresge et al) which includes a specific thermal internally conductive layer designed to prevent failure between the single chip and the carrier solder connections, and those between the carrier and base substrate (e.g., PCB) on which it is positioned. This patent is incorporated herein by reference.
Other examples of various electronic packages such as the above are shown and described in the following documents:
U.S. Patents4,882,454November 1989Peterson et al5,072,075December 1991Lee et al5,121,190June 1992Hsiao et al5,483,421January 1996Gedney et al5,615,087March 1997Wieloch5,661,089August 1997Wilson5,798,563August 1998Fielchenfeld et al5,838,063November 1998Sylvester5,894,173April 1999Jacobs et al5,900,675May 1999Appelt et al5,926,377July 1999Nakao et al5,982,630November 1999Bhatia
Foreign Patent DocumentsJP1-307294December 1989JP6-112271April 1994JP9-232376September 1997JP10-209347August 1998JP11-087560March 1999JP2000-022071January 2000JP2000-024150January 2000
In order to increase the operational characteristics of such modules, the addition of more than one chip to the upper surface of a chip substrate has been considered. However, due to the operating temperatures of such added chips, especially if placed in a closely spaced orientation, a much higher temperature compensating substrate material, ceramic, has usually been required, especially when the substrate having the chips is to be mounted on and coupled to an organic substrate such as a typical PCB. Examples are described in the following IBM Technical Disclosure Bulletins (TDBs):
July 1978Multi Chip Cooling Platepp 745–746February 1982Simultaneous Chip Placement - Multi-Chip Modulespp 4647–4649November 1987High Performance Multi-Chip Modulepp 437–439August 1988Low-Cost, High-Power, Multi-Chip Module Designpp 451–452September 1993Thermally Conductive Substrate Mounted Multi-Chip Module Cappp 623–624
The use of ceramic, however, poses many problems, a primary one of which is handling. Ceramic is a relatively brittle material capable of cracking and chipping if handled improperly during manufacture and shipping. Ceramic is also a relatively difficult material to process, especially to the multi-depth level where several individual layers of insulative and interconnecting conductive materials are needed to satisfy many operational requirements.
Chip carriers of non-ceramic material have been proposed, but these typically possess various drawbacks. In U.S. Pat. No. 5,574,630, for example, three chips are mounted on a substrate comprised of silica-filled polytetrafluoroethylene (PTFE) but require individual vias to pass through the carrier's entire thickness to connect to desired connections on the opposite side. Additionally, this structure in turn mandates utilization of a complex “power/ground assembly” of several layers having specific CTEs and other properties, thus resulting in a very expensive final assembly and one that is relatively difficult to construct.
Yet another non-ceramic substrate embodiment for having more than one chip thereon is described in U.S. Pat. No. 6,246,010. Unfortunately, the substrates require semiconductor chips which are extremely thin (less than 100 μm, preferably less than 50 μm, and “most preferably” less than 20 μm). Understandably, such thinned chips are incapable of adequately providing the much greater operational capabilities as required by today's more powerful chips (e.g., those of the application specific integrated circuit (ASIC) variety). Typically, such chips operate at much higher temperatures than other types (e.g., those of the dynamic random access memory (DRAM) variety).
In Ser. No. 10/354,000, cited above, there is defined a PCB which is capable of providing high speed interconnections between two or more components such as chips or modules (chip carriers) mounted thereon. This PCB is specifically designed to accommodate the increased operational requirements for electronic structures such as electronic modules which mount on the PCBs and are coupled together through the board's circuitry. One particular increase that this PCB accommodates is the need for higher frequency connections between the mounted components, which connections, as stated, occur through the underlying host PCB. Such connections are subjected to the detrimental effects, e.g., signal deterioration, caused by the inherent characteristics of such known PCB wiring. For example, signal deterioration is expressed in terms of either the “rise time” or the “fall time” of the signal's response to a step change. The deterioration of the signal can be quantified with the formula (Zo*C)/2, where Zo is the transmission line characteristic impedance, and C is the amount of the via capacitance. In a wire having a typical 50 ohm transmission line impedance, a plated through hole via having a capacitance of 4 pico farad (pf) would represent a 100 pico-second (ps) rise-time (or fall time) degradation, as compared to a 12.5 ps degradation with a 0.5 pf buried via of the present invention, as discussed below. This difference is significant in systems operation at 800 MHz or faster, where there are associated signal transition rates of 200 ps or faster.
A typical high performance PCB, prior to the one defined in Ser. No. 10/354,000, has not been able to provide wiring densities beyond a certain point due to limitations imposed by the direct current (DC) resistance maximum in connections between components (especially chips). Similarly, high speed signals demand wider lines than normal PCB lines to minimize the “skin effect” losses in long lines. To produce a PCB with all wide lines would be impractical, primarily because of the resulting excessive thickness needed for the final board. Such increased thicknesses are obviously unacceptable from a design standpoint.
Various PCBs are described in the following documents:
U.S. Patents4,902,610February 1990C. Shipley5,336,855September 1994J. Kahlert et al5,418,690May 1995R. Conn et al5,768,109June 1998J. Gulick et al5,891,869April 1999S. Lociuro et al5,894,517April 1999J. Hutchison et al6,023,211February 2000J. Somei6,075,423June 2000G. Saunders6,081,430June 2000G. La Rue6,146,202November 2000S. Ramey et al6,222,740April 2001K. Bovensiepen et al6,431,914August 2002T. Billman6,495,772December 2002D. Anstrom et alUS2002/0125967September 2002R. Garrett et al
Foreign Patent DocumentJP4025155A2January 1992O. Takashci
The teachings of these documents are incorporated herein by reference.
The unique characteristics of PCB in Ser. No. 10/354,000 allow it to be able to assure high frequency connections while still utilizing relatively standard PCB manufacturing processes to produce the final structure. In this pending application, incorporated herein by reference, a portion of the PCB is dedicated to utilizing relatively wider lines than the remaining, lower portion of the PCB, which includes lines and spacings known in the PCB field.
The use of such a structure or the like or a similar substrate of a material other than ceramic or not possessing the severe drawbacks of previous non-ceramic materials as mentioned above and which is capable of providing high speed or other effective coupling between two or more chips (especially high temperature chips such as ASIC chips) on one surface thereof, yet which can then be electrically coupled to a second underlying substrate such as a typical PCB to also couple said chips to the PCB's circuitry, is believed to constitute a significant advancement in the art.